The present invention relates to a programmable logic device including a plurality of logical elements and capable of arbitrarily programmably connecting these logical elements and, more particularly, to a programmable logic device capable of enhancing a switch using efficiency of wire groups by reducing the number of switching elements to be embedded.
A conventional programmable logic device 50 is, as illustrated in FIG. 9, composed of logical elements 51 arranged in array and wire groups 52, 53 each consisting of, e.g., 3 lengths of wires extending lengthwise or crosswise between these logical elements 51. Programmable wire switches 54 including switching elements for programmably connecting the vertical and horizontal wires are provided at intersections of the horizontally and vertically arranged wire groups 52 and 53, respectively. Further, I/O switches 55, 56 are provided for every vertical wire group 53 corresponding to the respective logical elements 51. Input signals from I/O switch 55 to the logical element 51 are transferred and received via, e.g., four wires 57 between the logical element 51 and the vertical wire group 53, while output signals from the logical element 51 to the I/O switch 56 are transferred and received via, e.g., two wires 58 between the logical element 51 and the vertical wire group 53.
The above-mentioned programmable wire switch (hereinafter simply referred to as a wire switch) 54 is required to include, for instance, at least 54 pieces of switching elements in the conventional device of FIG. 9 to programmably mutually connect all the wires extending in the vertical and horizontal directions. More specifically, as in a wiring example shown in FIG. 10, it is required that 9 switching elements 59 be provided for one combined wire thereof. As can be understood from a combination in the wiring example shown in FIG. 11, it follows that 54 pieces of switching elements 59 are needed. Namely, all the wires are connectable by the 54 switches. Note that in FIG. 11, the mark .largecircle. indicates the switching elements 59. This switching element 59 may involve the use of a memory-attached switching element 63, e.g., constructed by connecting a gate electrode of an NMOS transistor 61 to a simply illustrated SRAM cell 60 depicted in FIG. 8(a) and 8(b). All or a part of the wires are connectable or disconnectable from each other through the memory-attached switches, whereby arbitrary wiring can be programmably actualized.
The thus constructed programmable logic device 50 described above, however, presents the following problem. When connecting the signals between the adjacent logical elements 51, the number of the switching elements 59 in the wire switches 54 tends to increase for making the wire switches 54 connectable to the 3-way wires after the passage. That is, when the number of the connected elements increases, a parasitic capacity augments, or the area enlarges. This causes a defect in which the operation speed is decreased.